| 01 |
InlineFunctions |
Splices FunctionType.Inline bodies into every call site |
| 02 |
UnrollLoops |
Expands ForKind::Unroll loops at compile time |
| 03 |
CtrlFlowTransform |
Rewrites break / continue into structured control flow |
| 04 |
ConvertToSSA |
Converts to SSA form with variable renaming, phi nodes, and iter_args |
| 05 |
Simplify |
Folds arithmetic, shape expressions, and scalar constant bindings |
| 06 |
FlattenCallExpr |
Flattens nested call expressions into three-address form |
| 07 |
OutlineHierarchyScopes |
Outlines Hierarchy scopes into functions carrying level / role metadata |
| 08 |
OutlineGraphScopes |
Outlines pl.graph regions into FunctionType.Graph functions, converging the scope form with @pl.jit.graph |
| 09 |
OutlineIncoreScopes |
Outlines InCore scopes into separate functions |
| 10 |
OutlineClusterScopes |
Outlines Cluster scopes into Group functions and standalone Spmd scopes into Spmd functions |
| 11 |
ConvertTensorToTileOps |
Converts tensor ops to tile ops in InCore functions, updating orchestration call sites |
| 12 |
OptimizeOrchTensors |
Eliminates redundant orchestration allocations and improves data flow |
| 13 |
LowerCompositeOps |
Decomposes composite tile / distributed ops into primitives |
| 13 |
FlattenTileNdTo2D |
Flattens 3D+ tile operations to 2D by merging all but the last dimension |
| 15 |
BlockNzTensorViews |
Rewrites logical pl.NZ tensors into pto-isa's blocked rank-5 form and retargets their tile.load coordinates |
| 16 |
BlockMxScaleTensorViews |
Migrates logical MX scale views into canonical packed rank-5 physical form |
| 17 |
LegalizeTileCast |
Expands tile.cast pairs the ISA cannot emit as one instruction into the shortest native chain |
| 18 |
AutoTileMatmulL0 |
Picks an L0 tile shape (m, n, k) from the backend's L0 capacities and tiles matmuls to it |
| 19 |
CanonicalizeTileSlice |
Lowers tile.slice into the canonical tile.extract form |
| 20 |
InferTileMemorySpace |
Infers the on-chip MemorySpace of every tile and inserts tile.move to legalize mismatches |
| 21 |
InsertMxScaleAddr |
Inserts tile.tget_scale_addr before MX matmul consumers after memory spaces are resolved |
| 22 |
ResolveBackendOpLayouts |
Repairs backend-required tile layouts for elementwise ops |
| 23 |
LowerAutoVectorSplit |
Converts AUTO pl.split mixed InCore functions into the explicit split_aiv form |
| 24 |
ExpandMixedKernel |
Splits mixed InCore functions into separate AIC (Cube) and AIV (Vector) kernels |
| 25 |
InjectGMPipeBuffer |
Injects the __gm_pipe_buffer workspace for GM-routed cross-core pipes (Ascend910B) |
| 26 |
SplitVectorKernel |
Stamps split attributes and handles the no-split dual-AIV path |
| 27 |
StampTfreeSplit |
Copies each cross-core tpop's split and pipe id onto its matching tfree op |
| 28 |
NormalizeReturnOrder |
Reorders every InCore function's return tuple into the canonical order |
| 29 |
SkewCrossCorePipeline |
Software-pipelines mixed cube/vector loops so the two cores overlap |
| 30 |
LowerPipelineToSlots |
Rotates a pl.pipeline body through the slots of one allocation instead of replicating it (memory_planner=PTOAS) |
| 31 |
LowerPipelineLoops |
Replicates pl.pipeline(N, stage=F) bodies F times to enable ping-pong buffering |
| 32 |
CanonicalizeIOOrder |
Reorders pipeline-body statements along the scalar → load → compute → store ladder |
| 33 |
MaterializeTensorStrides |
Fills in the packed canonical stride for every tensor view that carries none |
| 34 |
InitMemRef |
Initializes MemRefs and creates alloc operations with unallocated addresses |
| 35 |
MaterializeSemanticAliases |
Forces buffers that program semantics require to be one allocation (loop-carry, in-place) |
| 36 |
MemoryReuse |
Reuses buffers by lifetime analysis and removes redundant allocs |
| 37 |
AllocateMemoryAddr |
Assigns real addresses to existing alloc operations |
| 38 |
FoldNoOpReshape |
Folds tile.reshape calls that change neither physical shape nor allocation |
| 39 |
FuseCreateAssembleToSlice |
Fuses tensor.create + tensor.assemble into one tensor.slice view |
| 40 |
LowerL2TensorCollectives |
Rewrites a managed collective written in a CHIP orchestration body into one local builtin AIV task, with no per-device fan-out and no nested L2 dispatch |
| 41 |
DeriveCallDirections |
Materializes wrapper ParamDirections, then derives a per-argument ArgDirection at every call |
| 42 |
AutoDeriveTaskDependencies |
Derives conservative task-to-task dependency edges |
| 43 |
ExpandManualPhaseFence |
Compresses profitable full-array TaskId dependencies in manual scopes |
| 44 |
SynthesizeAllReduceSignals |
Turns a host allreduce's optional signal into explicit internal signal IR |
| 45 |
MaterializeCommDomainScopes |
Assembles WindowBuffer and CommDomainScopeStmt wrappers in each host orchestration body |
| 46 |
LowerHostTensorCollectives |
Rewrites host-level tensor collectives into internal builtin chip dispatches |
| 47 |
MaterializeDistTensorCtx |
Materializes an explicit CommCtx parameter and argument per DistributedTensor |
| 48 |
LegalizeGraphBoundary |
Hoists the boundary scalars a Graph body derives out to its call sites, and rejects boundaries the host_build_graph runtime could not record |
| 49 |
MaterializeRuntimeScopes |
Inserts AUTO RuntimeScopeStmt nodes so orchestration codegen emits SIMPLER_SCOPE 1:1 |
| 50 |
ClassifyIterArgCarry |
Classifies each orchestration ForStmt iter_arg as a trivial alias or a materialised rebind carry |
| 51 |
InsertCommFence |
Marks each publishing write (region system.cacheinvalid + system.fence locally, fence only for a remote write, whole-GM for an opaque one) and each wait (whole-GM system.cacheinvalid); the notify itself gets no marker |
| 52 |
MaterializeValidShapeSymbols |
Turns each device-kernel valid_shape symbol the kernel cannot bind into a leading Scalar[INDEX] parameter, fed the caller's actual valid extent |