Catalog

Every operator family, one line each. Every name links into the API Reference for its signature — see Operations for why this page does not repeat them.

Reading the tables: the Reach column gives the shortest spelling that works. pl. means the name is available unqualified; pl.tile. / pl.tensor. mean the operator is level-specific. Names marked (t) are tile-only operators re-exported at top level for convenience — pl.load is pl.tile.load, not a dispatcher.

Creation

Operator	Reach	What it does
create_tensor	pl.	Allocate a DDR tensor. manual_dep=True opts it out of dependency tracking for its lifetime
create_tile	pl. (t)	Allocate an on-chip buffer
create_l1	pl. (t)	Allocate in L1 explicitly
full	pl.	A tensor filled with a constant
arange	pl.	Consecutive integers (tensor.ci)
random	pl.	Random-filled tensor
tri	pl. (t)	Lower- or upper-triangular mask tile; upper= picks the side, diagonal= shifts it, and only the valid region is written
const	pl.	A literal with an explicit dtype — see Directives
array.create	pl.array.	Allocate an on-core array

Data movement

Operator	Reach	What it does
load	pl. (t)	DDR → Vec (default) or Mat, via target_memory=
store	pl. (t)	On-chip → DDR
move	pl. (t)	On-chip → on-chip; the only path into Left / Right / Bias
reserve_buffer	pl.	Reserve a cross-core buffer
import_peer_buffer	pl.	Reference a peer core's buffer

See Memory and Data Movement for which moves are legal.

Elementwise arithmetic

Operator	Reach	What it does
add sub mul div	pl.	Binary arithmetic; a Python number on the right selects the scalar-operand form. For Tensor/Tensor and Tile/Tile div, high_precision=True selects the slower, higher-precision PTO path on A5; on A2/A3 PTO-ISA ignores it and returns the default result, which compilation warns about
neg abs recip	pl.	Unary negate, absolute value, reciprocal. For FP16/FP32 reciprocal, high_precision=True selects the slower, higher-precision PTO path on A5; on A2/A3 PTO-ISA ignores it and returns the default result, which compilation warns about
rem rems fmod fmods	pl.	Floor (rem*) and truncating (fmod*) remainder. Tensor operands must match shape and dtype; tile-tile operands must match physical and valid shapes. A2/A3 supports FP32/INT32 for rem* and FP32 for fmod*; every A2/A3 INT32 rem* source/scalar value must be in the inclusive PTO-ISA domain [-2^24, 2^24]. A2/A3 scalar forms require provably positive valid extents. Tile rem / rems scratch must have provably sufficient physical and valid capacity (two / one rows and all source columns) and must not overlap a live source on A2/A3. A5 accepts the wider frontend dtype union. high_precision=True is FP32 tile-tile only (defined on A5; accepted but ignored on A2/A3, where compilation warns)
addc subc addsc subsc	pl. (t)	Three-input add / subtract with carry operand
part_add part_mul part_max part_min	pl.	Partial (segmented) arithmetic

Math

Operator	Reach	What it does
exp log	pl.	Exponential, natural logarithm. For log, high_precision=True selects the slower, higher-precision PTO path on A5; on A2/A3 PTO-ISA ignores it and returns the default result, which compilation warns about
sqrt rsqrt	pl.	Square root; reciprocal square root. high_precision= is tensor-only and raises on a Tile — at tile level precision is selected by passing the scratch tile to pl.tile.rsqrt(src, tmp)
sin cos	pl.	Trigonometric

Comparison and selection

Operator	Reach	What it does
cmp cmps	pl.	Compare two operands / operand against a scalar
maximum minimum	pl.	Elementwise max / min of two operands
maximums minimums	pl. (t)	Elementwise max / min against a scalar
max min	pl. (t)	Scalar max / min of two values — not a tile reduction. To reduce a tile use row_max / col_max (and the min forms)
select	pl. (t)	out[i] = cond[i] ? a[i] : b[i]. The condition is a cmp / cmps mask (for a 0/1 value, compare it first: cmps(v, 0, cmp_type=1)); either branch may be a constant scalar. No scratch tile — it is filled in during lowering. Two tile branches must share shape, valid extents, and dtype
sel sels	pl. (t)	The 1:1 TSEL / TSELS forms behind select: mask required, scratch tile supplied by the caller

Activations

Operator	Reach	What it does
relu	pl. (t)	Rectified linear
prelu lrelu	pl. (t)	Parametric / leaky rectified linear

Bitwise

Operator	Reach	What it does
and_ or_ xor not_	pl.	Bitwise logic
ands ors xors	pl.	Bitwise logic against a scalar
shl shr	pl.	Shift left / right
shls shrs	pl.	Shift by a scalar amount

Reductions

Row reductions collapse the last axis; column reductions collapse the first.

Operator	Reach	What it does
row_sum row_prod row_max row_min	pl.	Reduce along a row
col_sum col_prod col_max col_min	pl.	Reduce along a column
row_argmax row_argmin	pl.	Index of the row extremum
col_argmax col_argmin	pl.	Index of the column extremum

Several reductions accept a tmp_tile argument. Passing one changes the reduction strategy (binary tree versus sequential), which changes floating-point association — the results differ within tolerance rather than being wrong. Reductions over a partially valid tile depend on the pad value; see Memory § valid shape.

Tensor pl.col_sum(x, is_binary=True) selects binary-tree reduction with compiler-managed scratch of shape [ceil(M/2), N] for static 2D inputs (full input shape otherwise). The default False preserves sequential reduction. This changes floating-point summation order and can increase UB usage. Tile callers continue to select the tree by passing tmp_tile.

Broadcast and expand

Operator	Reach	What it does
row_expand col_expand	pl.	Broadcast a reduced axis back to full width
row_expand_add row_expand_sub row_expand_mul	pl.	Broadcast fused with an arithmetic op
row_expand_div row_expand_max row_expand_min	pl.	Broadcast fused with division, max, or min
col_expand_add col_expand_sub col_expand_mul	pl.	Column-wise equivalents
col_expand_div col_expand_max col_expand_min	pl.	Column-wise division, max, and min
row_expand_expdif col_expand_expdif	pl.	Broadcast fused with exp(x - m) — the softmax kernel
expand_clone expands	pl.	Broadcast a value across a shape
fillpad fillpad_expand	pl.	Fill the invalid region; optionally broadcast in the same step

Shape and layout

Operator	Reach	What it does
reshape	pl.	Reinterpret dimensions
transpose	pl.	Transpose
slice	pl.	Sub-region; also written A[0:16, :]
concat	pl.	Join along an axis
assemble	pl.	Write a sub-region back; also written dst[i:i+16] = src
reinterpret_view	pl.	Reinterpret without moving data
set_validshape	pl.	Declare the meaningful region of a tile
cast	pl.	Convert dtype — may expand to a multi-hop chain, see LegalizeTileCast
dim	pl.	A tensor's runtime dimension
read write	pl.	Element access

Quantization

Operator	Reach	What it does
quant_mx	pl. (T/t)	Ascend950 block-32 dynamic quantization to FP8E4M3FN or packed fp4e2m1x2 data plus FP8E8M0 scales. FP4 requires FP16/BF16 input; axis1 returns [M,K/2], axis0 transposes [N,K] to [K,N/2]. quant_scale_alg="ocp" is the default; "nv" supports FP4 axis0. Tensor calls materialize GM data and MX-layout scales; tile calls stay on-chip. FP8 results can feed matmul_mx; native FP4 matmul is blocked by PTOAS v0.67 geometry (see types).
quant_mx_raw	pl.tile. (t)	Direct Ascend950 TQUANT with explicit max/scaling workspaces. Returns native FP4E2M1X2 or INT8 data and raw UINT8 exponent codes, without blocked MX scale packing. Axis1 accepts any positive row count and K divisible by 32 (64 for native FP4); source valid rows may be smaller than physical rows. Axis0 consumes source orientation directly and groups 32 valid rows; interleave=True interleaves exponent pairs for FP16/BF16 with rows divisible by 64.
tmov_x2zz	pl. (t)	Ascend950 exponent X-to-ZZ layout conversion (UINT8). Workspace tmp is write-only; axis1 needs dst_rows/dst_cols for ZZ [M,G] over flat TQUANT exp. Typically used via quant_mx lowering rather than directly

Linear algebra

Operator	Reach	What it does
matmul	pl.	Matrix multiply; a_trans= / b_trans= transpose an operand in place of a DN annotation
matmul_acc	pl.	Multiply-accumulate into an existing Acc tile
matmul_bias	pl. (t)	Multiply with a bias operand
batch_matmul	pl. (t)	Batched multiply, tile operands only. For tensors call pl.matmul — rank > 2 dispatches to tile.batch_matmul during lowering
gemv gemv_acc gemv_bias	pl. (t)	Matrix-vector forms
matmul_mx matmul_mx_acc matmul_mx_bias	pl. (T/t)	A5 MX block-scale multiply. Tensor matmul_mx consumes oriented 2D data/scale tensors and returns FP32; _acc / _bias remain tile-only. Data reaching the op must be FP8E4M3FN; native FP4×FP4 is unsupported

For phased GEMV accumulation, select producer phases with pl.AccPhase. A producer ending with pl.AccPhase.Final must be paired with a store using pl.STPhase.Final:

Here lhs0, rhs0, lhs1, and rhs1 are preloaded tiles, and output is the destination tensor.

partial = pl.tile.gemv(lhs0, rhs0, acc_phase=pl.AccPhase.Partial)
final = pl.tile.gemv_acc(partial, lhs1, rhs1, acc_phase=pl.AccPhase.Final)
pl.store(final, [0, 0], output, st_phase=pl.STPhase.Final)

Gather, scatter, sort

Operator	Reach	What it does
gather gather_row	pl.	Gather by index
paged_gather	pl.	Gather across a paged layout
gatherb	pl. (t)	Gather 32-byte blocks by UINT32 byte offset; one offset column expands to 32 / sizeof(output_dtype) elements
mgather	pl. (t)	Gather rows from a DDR tensor by index tile, with coalesce= and gather_oob= policies
scatter scatter_update	pl.	Scatter by index; update in place
mscatter	pl. (t)	Masked scatter
sort32 mrgsort	pl.	Sort a 32-element group; merge sorted runs

Block identity

Operator	Reach	What it does
get_block_idx	pl.	This block's index under pl.spmd
get_block_num	pl.	The block count
get_subblock_idx	pl.	The AIV lane index under pl.split_aiv

Cross-core transfer

The mixed-kernel surface — AIC and AIV cooperating inside one InCore function.

Operator	Reach	What it does
tpush_to_aiv tpush_to_aic	pl.	Push a tile to the peer core
tpop_from_aic tpop_from_aiv	pl.	Pop a tile pushed by the peer
tfree_to_aic tfree_to_aiv	pl.	Release a popped slot back to the producer
aic_initialize_pipe aiv_initialize_pipe	pl.	Set up the cross-core pipe
aiv_shard aic_gather	pl.	Shard across AIV lanes / gather back on AIC
AUTO	pl.	Sentinel for compiler-chosen pipe parameters

Push and pop must be paired, and each pop must be matched by a tfree. The tutorial covering this is Mixed kernels; the machine-level mechanics are in TPUSH/TPOP and ExpandMixedKernel.

Tasks and dependencies

Operator	Reach	What it does
submit spmd_submit	pl.	Dispatch a kernel and capture its producer TaskId
deps=	pl.at, captured inline pl.spmd	Add strict TaskId dependencies; deferred waiters use this same dependency path
no_dep	pl.	Exclude one argument of one task from dependency tracking
dump_tag	pl.	Mark a tensor for selective dump

See Scopes and Placement.

Arrays

Operator	Reach	What it does
array.create	pl.array.	Allocate
array.get_element	pl.array.	Read; also written arr[i]
array.update_element	pl.array.	Functional update; also written arr[i] = v

Distributed

pypto.language.distributed (conventionally pld) carries the collectives and remote primitives. Full reference at Distributed Programming; tutorial at distributed/00-model.md.

Capability Matrix

Operation	API	Modes	ReduceOp	Atomic	Supported dtypes	Notes
AllReduce	pld.tensor.allreduce	mesh (InCore + HOST), ring (InCore + HOST)	Sum, Max, Min, Prod (mesh); Sum only (HOST ring)	—	FP16, FP32 (mesh; hard compile-time check); HOST ring: FP32 only (4-byte)	Mesh: O(N) remote traffic per step. Ring: O(N/P) remote traffic per step, 2(P-1) steps.
AllGather	pld.tensor.allgather	—	—	—	FP32 only (HOST builtin); any GM dtype (InCore)	Push-based. Input and target must be different buffers.
ReduceScatter	pld.tensor.reduce_scatter	—	Sum, Max, Min, Prod (InCore); Sum only (HOST builtin)	—	FP32 only (HOST builtin); any GM dtype (InCore)	Every rank stages all NR chunks before the call.
Broadcast	pld.tensor.broadcast	—	—	—	FP32 only (HOST builtin); any GM dtype (InCore)	Root stages data before the call.
All-to-All	pld.tensor.all_to_all	—	—	—	FP32 only (HOST builtin); any GM dtype (InCore)	Personalized exchange. Input and target must be different buffers.
Barrier	pld.tensor.barrier	—	—	—	—	Signal is INT32, single-shot per call.
Put	pld.tensor.put	—	—	None_ / Add	All GM dtypes	dst must be window-bound. Supports chunked + pipelined staging.
Get	pld.tensor.get	—	—	—	All GM dtypes	src must be window-bound. Supports chunked + pipelined staging.
Notify	pld.system.notify	AtomicAdd / Set	—	—	—	Side-effect-only signal deposit.
Wait	pld.system.wait	Eq / Ge	—	—	—	Side-effect-only signal block.
Deferred Wait	pld.system.defer_wait	Ge only	—	—	INT32 signal	Register a monotonic counter condition without spinning the AIV; Simpler keeps the ordinary waiter TaskId incomplete and later work uses ordinary deps=[wait_tid].
Remote Load	pld.tile.remote_load	—	—	—	Any (tile)	Tile-level cross-rank load.
Remote Store	pld.tile.remote_store	—	—	—	Any (tile)	Tile-level cross-rank store.

Worked examples

One runnable file per family, for when the table entry is not enough:

Family	Example
Elementwise arithmetic	examples/beginner/02_elementwise.py
Scalar operands	examples/beginner/03_scalar_ops.py
Activations	examples/beginner/04_activation.py
Matmul	examples/beginner/05_matmul.py
Concatenation / assemble	examples/beginner/06_concat.py, examples/intermediate/05_assemble.py
Reductions	examples/intermediate/02_softmax.py, examples/intermediate/03_normalization.py
Cross-core transfer	examples/advanced/03_mixed_kernel.py
Tasks and dependencies	examples/intermediate/07_task_graph.py

See Also

• Choosing a Namespace — which of these spellings to use.
• IR Operators — the registry behind these names.
• PTOAS Operator Status — per-backend support.