PTO ISA¶
The hardware model and instruction semantics that PyPTO's generated code targets.
| Page | What it covers |
|---|---|
| Cluster Architecture | The 1 Cube + 2 buddy Vector core cluster and its flag-based synchronization |
| TPUSH/TPOP Instructions | Moving tiles between InCore kernels co-scheduled on Cube and Vector cores |
| Buffer Management | Where the TPUSH/TPOP ring buffer lives per platform — GM on A2/A3, consumer on-chip memory on A5 |
See Also¶
- SkewCrossCorePipeline Pass — the pass that software-pipelines cross-core loops onto this architecture.
- InjectGMPipeBuffer Pass — the GM-routed cross-core pipe workspace on Ascend910B.